Subject: Re: Begin-End / { } / < > ?
From: Paul Graham (pgraham@cadence.com)
Date: Mon Mar 04 2002 - 10:28:40 PST
> > We have all complained for years that Verilog requires begin-end while the
> > C-Language uses { }.
> >
> > I know we can't use { } because they are part of concatenation and replication.
The ambiguity arises from the use of a concatenation as an assignment target:
always @(d)
{
x ...
How should the parser treat this? It could turn out to be a begin/end:
always @(d)
{
x = d;
}
Or it could be the start of an assignment to a concatenation:
always @(d)
{
x, y, z} = d;
I can't think of any other cases where {/} used for begin/end would cause
ambiguities, and in practice most humans wouldn't be too confused by this
syntax. Still, it looks like it would be hard to fix the grammar to allow
this without ambiguity.
Paul
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