Re: FSM Section Vote?

Subject: Re: FSM Section Vote?
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Tue Apr 02 2002 - 17:34:14 PST


Yes, I did second the proposal, but I'd like to suggest a friendly amendment to the wording Cliff put in writing. 

AMENDED PROPOSAL: Remove the State Machine Section (section 9 in draft 4) from the SystemVerilog 3.0 LRM, and defer transition statement and operators for consideration in SystemVerilog 3.1.

I vote YES, as amended.

Assuming Cliff's proposal passes, I would also like to make a related proposal for e-mail vote (this will need a second).
PROPOSED: Remove "state" from the list of keywords in Annex B.  Leave "transition" in Annex B as a reserved word.

Stu

At 03:28 PM 4/2/2002, Clifford E. Cummings wrote:
Vassilios -

Did you get the message that we decided to conduct an email vote on the proposal to remove the FSM section from version 3.0 of the SystemVerilog Standard? I thought the Co-Design guys were going to ask you to conduct that vote and that voting would close on Friday, April 5th.

PROPOSAL: Remove the State Machine Section (section 9 in draft 4) from the SystemVerilog draft standard.
Proposed by: Cliff Cummings
Seconded by: Stu Sutherland (is this correct Stu?)

Regards - Cliff

BTW - my vote is:

Yes - remove the FSM section - Cliff
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