Subject: Re: FSM Section Vote?
From: Stefen Boyd (stefen@boyd.com)
Date: Tue Apr 02 2002 - 17:44:10 PST
At 05:34 PM 4/2/2002 -0800, Stuart Sutherland wrote:
>AMENDED PROPOSAL: Remove the State Machine Section (section 9 in draft 4)
>from the SystemVerilog 3.0 LRM, and defer transition statement and
>operators for consideration in SystemVerilog 3.1.
>
>I vote YES, as amended.
I also vote YES for the amended proposal.
Regards,
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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