Subject: Re: 26th Verilog++ Meeting Minutes 5/6/02
From: Adam Krolnik (krolnik@lsil.com)
Date: Tue May 07 2002 - 07:44:23 PDT
Good morning;
You write:
>Jayant (I think) mentioned the need to consider temporal
>logic. This must be considered alongside the various other
>committees also involved in this area, but should be at
>least discussed by this group
I too would like to see an action item for the assertion statements
to consider including:
o More support of Sugar CERE's (temporal regular expressions)
o Support for CERE's outside of the assert statements.
o Support for delay() or prev() functionality in assertion statements.
o Better support for overlapping assertions.
Also for the language:
o Support for first class part select operation {}[N:M] (lint removal)
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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