Subject: Re: .* and .name Implicit Port Declaration Proposal - 20020317
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Mar 20 2002 - 08:49:52 PST
Good morning Cliff;
Reading the first attachment, I don't understand these lines:
o "Any individual port in an implicitly instantiated module that does
not match both name and size of the net or bus of the upper-leve
module, shall be instantiated by name."
Are you saying that the ports referred here will not be implicitly
connected? That is different than saying it shall be instantiated
(really connected) by name.
I think it should say "will not be connected unless explicitly
connected by named port connection."
o "If implicit port connections are used to instantiate a sub-block,
the .* token must be placed first in the instantiated port list,
before any other named ports, if any, are listed."
Why do you want it first. I have used a tool where the token
was placed at the end. The thinking was that you would specify
the explicit named connections, you would specify the renaming
implicit connections, and then you would list the global connect
the rest...
E.g.
big_mod m1 (
.funny ({this, that, another}),
.error (), // ignore errors.
.alu(.*) (alu0_$1), // Connect the alu ports to alu0.
.* (*) // The rest.
This then allows for renaming implicit connections to be take priority
over choosing all the ports. I don't think there is a particular
reason for having it first or last since we don't allow renaming
implicit connections.
o "If a port on an instantiated sub-block is unconnected in the
upper-module, the port shall be explicitly listed as a named port
with empty parenthesis showing there is no connection."
Are you saying ports that don't connect to anything will be marked
as disconnected by verilog? Oh, covering up ambiguities, huh?!
I would rather see that any ports not connected by explicit or
implicit connections remain unconnected. This will allow lint
tools to point this out for engineers to review. If they really
want a port disconnected, they are free to specify that as such:
.unneeded_port (), // I know this is here, I am not connecting it.
Otherwise, I have to go and simulate to find out that oops, I'm missing
a name somewhere and this new port is now disconnected...
o "All nets or busses in the upper-level module that connect to
implicit ports must either be explicitly declared as a scalar net,
vector net, or as a port on the upper level module."
Should I bring up the question "do we need to explicitly declare
signals" debate? If the names must match in name and size, then you
know the size of the signal. If it only serves as a communication
medium for two sub modules, then requiring its explicit definition
becomes a burden when adding communication to two modules...
I would like to see an additional example using the interface
feature of SystemVerilog with this feature to show that they do
work together usefully.
o This is about forbidding the mixing of the .name style and the
.* style.
The reasoning here for the prevention of mixing these
two features here is unique in the entire document. If a group
intends to make stylistic choices, they will use a style checking
tool to enfoce their choices. To add this to the System Verilog
specification seems out of place. While I have no disagreement
with recommending that one does not mix the features, I don't
agree that that it should be explicitly required by vendors to
prevent this usage. This should be the job of other tools.
Thanks
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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