Subject: .* and .name Implicit Port Declaration Proposal - 20020317
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Sun Mar 17 2002 - 09:25:00 PST
Hi, All -
Stu informs me that at Thursday's meeting, a new set of deadlines were set
and that I am required to make the .* & .name proposal by tomorrow (Monday
- three days notice). I sent out the original proposal on December 13th,
apparently ignored. At a recent conference call, Anders asked for a
friendly amendment to include the .name syntax.
I cannot be on the call this Monday (I fly out of town again tonight). I
will try to rearrange my schedule next week to be on that call. I hope my
proposals receive reasonable consideration in my absence or that final
voting can be done when I am present to defend my proposals. Scheduling
meetings on very short notice and issuing proposal deadline ultimatums for
topics I have previously spent many engineer-hours developing and had
previously sent (in December - both FSMs and interfaces), leaves me less
than pleased.
I have recently spent days putting together another FSM example with
accompanying FSM coding styles, thinking this was a high priority (the
examples were sent out weeks ago). Apparently, I should have spent the time
first on the implicit ports proposals.
Below are some of my notes and proposed rules for implicit ports. I am also
attaching a
re-send (with some updates, including Verilog-2001 modified BNF) showing
some of the changes I propose. I will make further wording proposals and
add .name examples if my work is not shot down on Monday; otherwise, what's
the point?
Regards - Cliff
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