Subject: Re: Unconnected inputs
From: Michael McNamara (mac@verisity.com)
Date: Mon Mar 25 2002 - 11:24:14 PST
Ah, yes. VCS appears to initializing wires at time 0, not at compile
time (as it did when I left!!).
I believe I ran into this in 1996 when I was a consultant at SGI or
Chromatic research....
Adam Krolnik writes:
>
>
> Hi Mac,
>
> Here is why I asked the question:
>
> Add this to your program:
>
> initial $display ("At 0, A is %b B is %b C is %b", a,b,c);
>
>
> vcs ...
> ...
> Compiler version 6.0; Runtime version 6.0; Mar 25 13:11 2002
>
> At 0, A is x B is xxxxxxxx C is zzzzzzzz
> A is z B is zzzzzzzz C is zzzzzzzz
> V C S S i m u l a t i o n R e p o r t
> Time: 10
>
> Modeltech 5.5: (vlog uncon.v -R -do 'run -all' -c)
> # 5.5
>
> # vsim -do {run -all} -c uncon_input
> # // Warning: License will expire soon.
> # Loading work.uncon_input
> # run -all
> # At 0, A is z B is zzzzzzzz C is zzzzzzzz
> # A is z B is zzzzzzzz C is zzzzzzzz
>
> Funny...
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
XL says:
Highest level modules:
uncon_input
0 A is z B is zzzzzzzz C is zzzzzzzz
10 A is z B is zzzzzzzz C is zzzzzzzz
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.2 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of VERILOG-XL 3.10.s010 Mar 25, 2002 11:23:51
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