Subject: Re: Unconnected inputs
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Mar 25 2002 - 11:37:09 PST
Adam -
Could you try this again except use:
initial $strobe ("At 0, A is %b B is %b C is %b", a, b, c);
Doing a $display of varA in any time step in a separate procedural block
and not immediately after the assignment to the varA variable in the same
procedural block is a Verilog race condition. In this example, doing a
$display at time 0 of any Verilog variable is a race condition.
For these reasons, I always recommend that if you intend to assert and
recognize a reset at time zero, you should do it by making the time-0 reset
assignment using a nonblocking assignment (to permit all procedural blocks
to become active before the reset assignment completes and triggers the
appropriate procedural blocks).
Regards - Cliff
At 11:24 AM 3/25/02 -0800, Michael McNamara wrote:
>Ah, yes. VCS appears to initializing wires at time 0, not at compile
>time (as it did when I left!!).
>
>I believe I ran into this in 1996 when I was a consultant at SGI or
>Chromatic research....
>
>Adam Krolnik writes:
> >
> >
> > Hi Mac,
> >
> > Here is why I asked the question:
> >
> > Add this to your program:
> >
> > initial $display ("At 0, A is %b B is %b C is %b", a,b,c);
> >
> >
> > vcs ...
> > ...
> > Compiler version 6.0; Runtime version 6.0; Mar 25 13:11 2002
> >
> > At 0, A is x B is xxxxxxxx C is zzzzzzzz
> > A is z B is zzzzzzzz C is zzzzzzzz
> > V C S S i m u l a t i o n R e p o r t
> > Time: 10
> >
> > Modeltech 5.5: (vlog uncon.v -R -do 'run -all' -c)
> > # 5.5
> >
> > # vsim -do {run -all} -c uncon_input
> > # // Warning: License will expire soon.
> > # Loading work.uncon_input
> > # run -all
> > # At 0, A is z B is zzzzzzzz C is zzzzzzzz
> > # A is z B is zzzzzzzz C is zzzzzzzz
> >
> > Funny...
> >
> > Adam Krolnik
> > Verification Mgr.
> > LSI Logic Corp.
> > Plano TX. 75074
> >
>
>
>XL says:
>
>Highest level modules:
>uncon_input
>
> 0 A is z B is zzzzzzzz C is zzzzzzzz
> 10 A is z B is zzzzzzzz C is zzzzzzzz
>0 simulation events (use +profile or +listcounts option to count)
>CPU time: 0.2 secs to compile + 0.0 secs to link + 0.0 secs in simulation
>End of VERILOG-XL 3.10.s010 Mar 25, 2002 11:23:51
//*****************************************************************//
// Cliff Cummings Phone: 503-641-8446 //
// Sunburst Design, Inc. FAX: 503-641-8486 //
// 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
// PMB 501 Web: www.sunburst-design.com //
// Beaverton, OR 97005 //
// //
// Expert Verilog, Synthesis and Verification Training //
//*****************************************************************//
This archive was generated by hypermail 2b28 : Mon Mar 25 2002 - 11:38:19 PST