Subject: Re: Proposal for array types
From: Paul Graham (pgraham@cadence.com)
Date: Tue Apr 09 2002 - 07:06:44 PDT
>
> In Verilog it is legal to write reg [0:0] r;
>
> What should $increment return?
1.
Think about how you would write a for loop that loops from 0 up to some
value >= 0. What would you use as an increment step? You would write:
for (i = 0; i <= TOP; i = i + 1)
This works even if TOP == 0.
I guess the question is whether [0:0] is an ascending or descending range.
One could adopt the convention that a range is ascending if $left >= $right.
VHDL defines "ascending" syntactically. A to B is ascending, regardless of
the values of A and B, while A downto B is descending.
Paul
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