Subject: .* and .name proposals - Cliff votes yes
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Mar 21 2002 - 17:02:07 PST
I just got back into town today. My email has been down.
I want my vote in favor of the following two proposals to be counted:
.name implicit port connections - YES
.* implicit port connections - YES
Suggestions that the .* proposal needs further discussion and should be
postponed to version 3.1 are unwarranted. This proposal is not rocket
science. The only two points that are remotely debatable are:
1 - Should top-level net declarations be required? The proposal calls for
all top-level declarations to be made. One user at HDLCON suggested that
not even these declarations should be required. Version 3.1 can remove this
requirement if the committee deems this argument to be valid.
2 - Should .* be required to be listed first in the port list? The proposal
requires .* to be listed first. One person on this reflector suggested that
it be listed last. I still like the idea that it be listed first to
indicate that this instance is going to use this format and that any mixing
with the .name syntax will be an immediate syntax error. I am open to
friendly amendments that change this requirement in the next couple of weeks.
Although the .name syntax is a vast improvement over current named port
connections, it will only turn a 10-page named-port-connection top-level
design into a 6-page top-level design. When was the last time you did a
detailed review all of the port connections of a large top-level module.
Use .* and that top-level design goes to about two pages and shows all of
the CONNECTION-EXCEPTIONS. Now that is both concise and valuable.
We are considering much more complex proposals, including some rather
interesting assertions, that probably should require more thought than the
very conceptually-simple .* connections. I don't care if Superlog can add
this feature by DAC or not. I just want to be on record that this feature
should be added.
Remember - Intel's IHDL has had a long history of success using this
capability. It will be an extremely nice shorthand to the SystemVerilog
language and a huge selling point to those who are going for abstraction
through abbreviated syntax (abstraction usually comes from a higher level
abbreviated syntax).
Just wait until Version 3.1 when I propose the following syntax:
connect [range] net1 = net2 = net3 = net4; // must all be scalar or must
all have the same size
To permit even more widespread value to the .name and .* syntax
enhancements. Then you will be able to use .name and .* more often!
Regards - Cliff
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