Subject: Addendum to section 4.2: signed packed arrays
From: Paul Graham (pgraham@cadence.com)
Date: Mon May 06 2002 - 13:25:20 PDT
We need to change the third paragraph in section 4.2 on packed arrays to
reflect a clarification from Pete Flake. The existing text reads:
If a packed array is declared as signed, then the array viewed as a
single vector shall be signed, as in Verilog 2001. Note that Verilog
2001 defines that a part selects of an array is unsigned.
This paragraph should read:
When a packed array is declared as signed then the individual elements
of the array are signed, and the array as a whole, when viewed as a
bit-vector, is signed.
The sentence about part selets of an array is irrelevant here and should be
dropped.
Paul
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