Subject: Fwd: SystemVerilog draft 6
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Fri Apr 19 2002 - 18:15:44 PDT
All,
I sent out draft 6 about a half hour ago, but have not seen it come back to
me through the reflector. It could be the attachment is too big. Just in
case you did not receive the first message with the attachment, I've placed
the draft on my web site. You can download it from:
http://www.sutherland-hdl.com/download/SystemVerilog_draft6.pdf
Stu
>Date: Fri, 19 Apr 2002 16:51:43 -0700
>To: vlog-pp@eda.org
>From: Stuart Sutherland <stuart@sutherland-hdl.com>
>Subject: SystemVerilog draft 6
>
>All,
>
>Draft 6 is attached. This draft incorporates all changes approved through
>meeting 23 (15 Apr 2002). The full BNF and assertions sections have been
>added. The document is now in "clean up" phase. Please carefully review
>your favorite topics for both technical correctness as well as reasonable
>grammar, spelling and punctuation (reasonable for engineers,
>anyway). Also be sure to look for those infamous "Editor note"
>boxes. I'd like to get all those resolved in our next meeting, Monday 22 Apr.
>
>I'm going to get some sleep now..................
>
>Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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