Subject: Re: SystemVerilog draft 6 - structs,unions & packing.
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Apr 22 2002 - 12:05:28 PDT
Knowing packing order for data in structures is essential for co-simulating hardware
and software. It should be possible to define register layout (bit fields) in a C struct
used by embedded software and have it map consistently to hardware described in
SystemVerilog.
Currently I'm simulating a little-endian ARM 7 system on big-endian Sparc machines.
If SystemVerilog defaulted to big-endian packing of its structures because it was being
run on Sparc, any mapping I set up between SV structs and C structs will not run the
same if I then run the simulation on a Linux/X86 simulator.
SystemVerilog should by default be a simulation platform independent description.
Previous posts:
Vlog-pp - Verilog++: Unions - overlaying bits & logic
Vlog-pp - Verilog++: Re: Unions - overlaying bits & logic
A secondary issue is whether the X/Z information in logic types is orthogonal to the
1/0 values, if it is you should be able to create a union of C and SV types such that
you can extract the C-type 1/0 value, e.g.:
union {
int C;
logic [31:0] SV;
} csvi;
....
csvi.SV = 32'hDEADBEAF;
csvi.SV = 32'hXXXXXXXX; // X status of bits is othogonal
....
printf ("0x%08X\n",cvsi.C); // C prints 0xDEADBEEF
Currently that doesn't appear to be excluded in the LRM, but makes a huge difference
in how you would approach implementation.
Previous post:
Vlog-pp - Verilog++: Integer types in BNF
There is also no description of how packing "left to right" in System Verilog relates to C packing.
Note: C distinguishes packed and unpacked with the ':' field syntax, e.g.:
typedef struct { // packed
int exp:8,
mag:16;
} exp_mag;
is not the same as:
typedef struct { // unpacked
char exp;
short mag;
} exp_mag;
- "mag" and "exp" will pack differently depending on endianess and whether shorts can be
byte aligned.
Kev.
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