Subject: RE: SystemVerilog draft 6 - structs,unions & packing.
From: David Smith (david_smith@avanticorp.com)
Date: Mon Apr 22 2002 - 13:33:32 PDT
It seems to me that the issue of C interface is not part of the language. It is not defined anywhere in the LRM. It is defined, within limits, within the VPI/PLI interface. If this is the interface to access data then when the VPI/PLI interface is defined it needs to be handled.
One comment is that the packing order used within the simulator does NOT have to match the packing order used in the C code. Since this is different on different systems it will always be inefficient for one of them. The code that supports the C API can choose to guarantee that the packing is always correct for the platform it is on. All this means is that the packing of the bits used within the language must be consistently used within the language.
So, where is the C interface designed that will see this data?
Regards
David
David W. Smith
Architect
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-----Original Message-----
From: Kevin Cameron [mailto:Kevin.Cameron@nsc.com]
Sent: Monday, April 22, 2002 12:05 PM
To: vlog-pp@eda.org
Cc: flake@co-design.com
Subject: Re: SystemVerilog draft 6 - structs,unions & packing.
Knowing packing order for data in structures is essential for co-simulating hardware
and software. It should be possible to define register layout (bit fields) in a C struct
used by embedded software and have it map consistently to hardware described in
SystemVerilog.
Currently I'm simulating a little-endian ARM 7 system on big-endian Sparc machines.
If SystemVerilog defaulted to big-endian packing of its structures because it was being
run on Sparc, any mapping I set up between SV structs and C structs will not run the
same if I then run the simulation on a Linux/X86 simulator.
SystemVerilog should by default be a simulation platform independent description.
Previous posts:
Vlog-pp - Verilog++: <http://www.eda.org/vlog-pp/hm/0457.html> Unions - overlaying bits & logic
Vlog-pp - Verilog++: Re: Unions <http://www.eda.org/vlog-pp/hm/0487.html> - overlaying bits & logic
A secondary issue is whether the X/Z information in logic types is orthogonal to the
1/0 values, if it is you should be able to create a union of C and SV types such that
you can extract the C-type 1/0 value, e.g.:
union {
int C;
logic [31:0] SV;
} csvi;
....
csvi.SV = 32'hDEADBEAF;
csvi.SV = 32'hXXXXXXXX; // X status of bits is othogonal
....
printf ("0x%08X\n",cvsi.C); // C prints 0xDEADBEEF
Currently that doesn't appear to be excluded in the LRM, but makes a huge difference
in how you would approach implementation.
Previous post:
Vlog-pp - <http://www.eda.org/vlog-pp/hm/0530.html> Verilog++: Integer types in BNF
There is also no description of how packing "left to right" in System Verilog relates to C packing.
Note: C distinguishes packed and unpacked with the ':' field syntax, e.g.:
typedef struct { // packed
int exp:8,
mag:16;
} exp_mag;
is not the same as:
typedef struct { // unpacked
char exp;
short mag;
} exp_mag;
- "mag" and "exp" will pack differently depending on endianess and whether shorts can be
byte aligned.
Kev.
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