Subject: Re: "universal" logic type
From: Alec Stanculescu (alec@fintronic.com)
Date: Tue Jan 22 2002 - 19:31:40 PST
>
> At 10:31 AM 1/21/2002 -0800, Alec Stanculescu wrote:
> >Question: what is the advantage of not giving a special name (wire or
> >reg) to a an object which we know will be used in a certain way. The
> >more information we can capture in a declarative way the better of we
> >are (in general:-).
>
> Alec,
>
> Thanks for your feedback (and others as well). I started
> wanting a universal type when I noticed that the logic
> type (and other new types like bit) could be used in a
> continuous assignment... Yes, there are times that I want
> to be specific, but wire vs reg is more of a hassle then
> a benefit.
>
> The difference is really in how we use it then
> how it's declared. We know we want to use an object
> as a wire until we change our mind and use it in
> a procedural assignment... and are forced to change
> the declaration just to accommodate the change in usage.
>
> Stefen
>
>
> --------------------
> Stefen Boyd Boyd Technology, Inc.
> stefen@BoydTechInc.com (408)739-BOYD
> www.BoydTechInc.com (408)739-1402 (fax)
>
Stefen,
I agree with you that more thought ought to be given to this issue.
First I propose, as Peter suggested, to separate the issues of value
of object and other properties such as resolution function, and
context in which it can be assigned from.
Second, we should enumerate perceived problems with these objects.
1. Peter rephrased Stefen's complaint into "why can't write into a reg
from a continuous assignment?" Do you agree with this restatement
Stefen?
2. Personaly, I do not like the fact that a reg is not a register for
synthesis purposes. I believe that there should be objects called
2.1 wires that have resolution functions associated with them,
2.2 variables (this is present in VHDL) which do not have resolution
functions associated to them(or a resolution function that resolves
to the latest value driven by any of the drivers).
2.3 registers which do not have resolution functions associated to
them and which should be synthesized as registers. They should have
a predefined operation reset to a specific value and should allow
the clock to be specified in their declaration. The reset operation
is asynchronous as opposed to all other assignments that are
synchronous with the declared clock (posedge or negedge as declared).
Multiple clocks associated to one reg could be supported as well.
All objects (wires, var, and reg) can be written from both continuous
and procedural assigns. The values that these objects have are:
wire - same as in Verilog
var - 0, 1, x, z
reg - 0, 1, x, u (where u is uninitialized and is otherwise the same
as x).
I understand that the Verilog legacy may not allow us to do this, but
I am trying to understand better what it is that we should want.
Regards,
Alec
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