Subject: Re: Adding Regular Expressions to Instantiation?
From: Peter Flake (flake@co-design.com)
Date: Wed Feb 27 2002 - 01:44:30 PST
Hi, Cliff,
As a pre-processor, this is OK because it can be debugged by reading the
pre-processor output.
Even so, I think it is challenging for a novice to use the regular expressions.
Without a pre-processor it would be much harder to debug. Let us wait until
we get used to 'generate'.
Regards,
Peter.
At 12:07 PM 2/26/02 -0800, Clifford E. Cummings wrote:
>Hi, All -
>
>Adam Krolnik brought this paper from Lionel Bening to my attention about
>using regular expressions while instantiating modules and ports.
>
>The paper is six pages long and is attached as a PDF attachment.
>
>Is this capability worth considering for SystemVerilog? Looks interesting
>to me. I'm wondering if the tool vendors would consider it.
>
>Regards - Cliff
>
>>Sender: bening@rsn.hp.com
>>Date: Tue, 26 Feb 2002 13:53:38 -0600
>>From: Lionel Bening <bening@rsn.hp.com>
>>
>>"Clifford E. Cummings" wrote:
>>
>> > Hi, Lionel -
>> >
>> > I am part of an Accellera group that is working on SystemVerilog, the next
>> > version of Verilog with some exciting enhancements.
>> >
>> > We are about to pass two proposals related to implicit port instantiation.
>> > The first is the ability to instantiate modules with .name ports without
>> > requiring .name(name) lists when the port names match the connecting
>> > signals in both name and size.
>> >
>> > Example:
>> >
>> > module dff (output reg q, input d, clk, rst_n);
>> >
>> > always @(posedge clk or negedge rst_n)
>> > if (!rst_n) q <= 0;
>> > else q <= d;
>> > endmodule
>> >
>> > module testbench;
>> > reg d, clk, rst_n;
>> > wire out1;
>> > // ...
>> >
>> > // instantiate the dff
>> > dff d1 (.q(out1), .d, .clk, .rst_n);
>> > endmodule
>> >
>> > The second proposal is to use .* implicit instantiation to permit
>> ports and
>> > signals to be automatically connected if the port matches the signal in
>> > both name and size. Using the same dff module from above, the testbench
>> > with instantiation would be:
>> >
>> > module testbench;
>> > reg d, clk, rst_n;
>> > wire out1;
>> > // ...
>> >
>> > // instantiate the dff
>> > dff d1 (.*, .q(out1));
>> > endmodule
>> >
>> > Adam Krolnik has brought to my attention the paper that you and Robert
>> > Pflederer did at HDLCON last year using regular expressions to facilitate
>> > an interesting means of instantiating devices. This may be too much to
>> > propose at this time, but I would at least like the rest of the committee
>> > to look over what you wrote and see if there is enough vendor interest to
>> > make regular expression interconnect and instantiation a part of
>> SystemVerilog.
>> >
>> > Would you mind if I distribute a PDF version of your paper to the rest of
>> > the committee with the recommendation that the technique be explored? Adam
>> > has sent me a PDF version that I could distribute, unless you have a
>> > different version that you would rather have distributed.
>> >
>> > Unfortunately I need a quick response since we are on a fast-track to
>> > approve what I have already proposed.
>> >
>> > Regards - Cliff Cummings
>>
>>
>>Hi Cliff,
>>
>>Sure, go ahead and pass around the .pdf . I don't
>>have a different version.
>>
>>The regular expression interconnection was fun to write,
>>and our Verilog writers have used it extensively.
>>When I tried to back it out of our tools set for
>>the next project, our engineers said "You can't do that!"
>>
>>Vendor support for this technology would be
>>welcome, by designers here and elsewhere.
>>
>>On some other technology business, I found my
>>way yesterday to the person who handles
>>intellectual property licensing for HP. So if
>>the regular expression-based interconnection
>>technology needs transfer to Accellera or EDA
>>Vendor(s), it is a possibility.
>>
>>Lionel
>>
>>--
>>bening@rsn.hp.com
>>(972)497-4013 Office
>>(972)497-4500 Fax
>>http://www.verifiableRTL.com
>>http://www.lionelbening.org
>
>
>
>
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