Subject: Re: arrays in SystemVerilog
From: Paul Graham (pgraham@cadence.com)
Date: Tue Feb 26 2002 - 13:21:28 PST
Peter,
> >It is possible to assign a whole array if all its dimensions are packed,
> >but not ossible to assign a whole array with unpacked dimensions. Why not?
>
> This is a simulation efficiency issue, rather than fundamental to the
> language. It makes it harder to copy a megabyte.
An implementation must be able to support a packed array of 2**16 bits or
more. So it is still possible to copy 8Kb with a single assignment (more if
the simulator supports it):
reg [65535:0] x, y;
x = y; // legal, copies 8K bytes
Yet it's not possible to copy 4 bytes with an unpacked array assignment:
reg [7:0] x[3:0], y[3:0];
x = y; // illegal
If want the simulator or synthesis tool to do a lot of work with just a few
kestrokes, just instantiate a large divider! The point is not to disallow
concise expression of computationally expensive tasks, is it?
As I understand, the intent of a packed array is to allow a bit-vector to be
treated also as an array of smaller bit-vectors. Presumably then it is
possible to convert between bit-vector and packed array like this:
reg [3:0][7:0] x;
reg [31:0] y;
y = x;
x = y;
The only real difference between x and y in the above example is that it's
more convenient to access sub-fields of x:
x[1] // instead of y[15:8]
Regarding arithmetic ops on arrays, what I have in mind is something like this:
reg [7:0] x[3:0], y[3:0], z[3:0];
z = x + y;
This is basically matrix addition:
z[i] = x[i] + y[i]; // for i in 3..0
The idea is to use arrays to express parallelism. Once an array operation
is unrolled, so to speak, the normal Verilog rules for bit-width and sign
are applied to each sub-assignment.
Paul
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