Subject: Re: June 5th Meeting for HDL+ committee meeting -- PLEASE RSVP.
From: Harry Foster (harry@verplex.com)
Date: Wed May 22 2002 - 02:14:27 PDT
Hi Vassilios,
Unfortunately I will not be in the Bay area the first week of June. I can
set some time aside to participate on the phone. However, a 7 hour phone
call would not be practical for me the week before DAC. Will there be a
schedule of topics so I could know the appropriate time to call in?
-Harry
----- Original Message -----
From: <Vassilios.Gerousis@Infineon.Com>
To: <vlog-pp@eda.org>; <assertion@eda.org>
Sent: Wednesday, May 22, 2002 1:40 AM
Subject: June 5th Meeting for HDL+ committee meeting -- PLEASE RSVP.
> Dear members of Verilog++ and Assertions,
> I need to get counts of people who will attend the meeting in person or by
phone.
> We plan to organize the 3.1 of SystemVerilog release. It will be a full
day from 9:00 until 4:00 PM. The main focus is to identify the focus of 3.1
release. He will have special presentations on new donations for the support
of SystemVerilog 3.1.
> I will send details in few days.
>
> Best Regards
>
> Vassilios
>
> --------------------------------------------------------------------------
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> Dr. Vassilios Gerousis Infineon Technologies
> DAT CAD, MchB
> Telephone: +49-89-234-21342 BalanSt. 73
> Fax: +49-89-234-23650 D-81541 Munich
> email: Vassilios.Gerousis@infineon.com Germany
> Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> --------------------------------------------------------------------------
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>
>
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