Subject: June 5th Meeting for HDL+ committee meeting -- PLEASE RSVP.
From: Vassilios.Gerousis@Infineon.Com
Date: Tue May 21 2002 - 23:40:09 PDT
Dear members of Verilog++ and Assertions,
I need to get counts of people who will attend the meeting in person or by phone.
We plan to organize the 3.1 of SystemVerilog release. It will be a full day from 9:00 until 4:00 PM. The main focus is to identify the focus of 3.1 release. He will have special presentations on new donations for the support of SystemVerilog 3.1.
I will send details in few days.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
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Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
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