Subject: additional minutes
From: Erich Marschner (erichm@cadence.com)
Date: Mon May 20 2002 - 11:19:16 PDT
Additional notes (to be appended to Dave Kelf's)
(continuing review of Paul's comments...)
7.2 - error in comment - disregard
8.1 - beautification - skip
8.3 - is {} a SuperLog expression? yes - strike the statement
"With SystemVerilog, null or void or {} are also false."
8.9 - typo in example - already caught
10.2 - remove port and port_event; connect task prototypes with interfaces
Vassilios -
Stu to issue list of changes to draft 8 made today by end of week
no meeting on the 27th - Memorial Day
further discussions (e.g., regarding issues) via email
full-day meeting on June 5th in San Jose - with dialin support
BOF meeting at DAC on Wednesday (though few committee members will be at DAC)
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Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
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