Subject: FW: Time To Act And Stop The Politics
From: Vassilios.Gerousis@Infineon.Com
Date: Mon May 20 2002 - 05:04:17 PDT
To Verilog++ and Assertion committee members,
During this weekend, Cadence Board Member, Grant Martin is questioning the condition of the current draft of SystemVerilog 3.0. He is proposing to delay the standard which you, including Paul Graham of Cadence has accepted this version as is. Mac and Dennis have sent emails supporting this current draft and the final 100% decision vote of this committee.
I have sent you earlier his first email with my response attached to it. Despite the support of Mac and Dennis to the current process, Grant sent two additional emails that insist on delaying the standard.
This not an IEEE process, were we have to do two or more cycles of technical reviews and adjustment. For an IEEE standard this is important to do. For an Accellera standard, we must put a version that the technical agrees with to the industry. Accellera promote the concept of tool prototypes and this help to bring back to 3.1 practical feedback than just opinions.
You can find my final message to the board below. I know that Cadence is trying to delay the standardization of SystemVerilog during DAC. They are welcome to vote no on the current draft and reject this excellent work that OVI/Accellera ever did.
I am proud to be the chairman of such a distinguished group of people. All of us have done their best to make Draft 8 the best we can offer. I know that every person here is proud of this achievement. We have done the best in engineering and management judgement on all technical issue brought directly to this committee.
All Cadence experts that are currently part of this committee and to the new ones who want to join, please come and debate your views on a technical basis through committee. We welcome your participation and help in making 3.1 a better standard. If any of you, can show today, that any of the issues pointed out by Cadence Board member is a show stopper for 3.0, I will give you a chance to state your points of views.
I hope that the board will continue its process and not listen to the pure delay tactics that Cadence representative is trying to do. However, this committee is willing to listen to the technical arguments of Cadence. We are the better judge of their validity and not the Accellera board.
Consider this an open welcome to the new experts from Cadence.
Best Regards
Vassilios
-----Original Message-----
From: Vassilios.Gerousis@infineon.com
[mailto:Vassilios.Gerousis@infineon.com]
Sent: Monday, May 20, 2002 1:28 PM
To: accellera_bod@accellera.org
Subject: Time To Act And Stop The Politics
Dear Accellera Board Members,
You have appointed me as the technical chairman for all committees within Accellera.
I have also been the chairman for Verilog++ committee, where I have followed an extremely fair but strict process. We have been working on the same process for standardization since the inception of OVI/Accellera. We did improvement on this process multiple times. There is always improvement required in any action we do. There is nothing in this world that is perfect. For the same reason, there is no perfect standard either. We do standards by design and not by injecting havoc and chaos. At every milestone, the committee has done its best job and provided the best it can deliver.
At any point during the year of SystemVerilog, Cadence had the chance to participate in the technical activities. Also the Cadence board member, Grant, had every chance to change the standardization process and the SystemVerilog Roadmap at any of the board meeting during the last year. The easiest, is to send his experts to the committee and do it through the committee and not through the board. They can interrupt the committee activities and discuss this today at the May 20 meeting. However, the standardization process must continue as planned and as has been pointed out by both Accellera Chairman and also Vice Chairman.
The Accellera Board has appointed me to provide technical assessment and also the Accellera board must TRUST the committee technical activities. Here are the facts:
1- The committee has voted 100% (National is not an Accellera member) to accept the current Draft 8, as the standard for SystemVerilog based on technical merits. They have provided their technical opinion to the board as a strong technical recommendation for the board to consider.
a- This includes Cadence vote, Paul Graham, to accept the LRM at the technical level AS IS.
2- The committee has made the best "technical" judgement to postpone 10 or more technical issues for consideration of 3.1 release. Again this is done through a voting process on every one of those technical issues. This is again been communicated as the roadmap of every standard we did.
3- SystemVerilog 3.0 Draft 8 is the best technical LRM OVI and Accellera has ever published.
4- Every draft that we have given to the board, followed the same process and also had the same compromise of what to include and not to include. Examples are:
a- Verilog-AMS 2.0 has 98 technical issues. In fact, some of them are dis-functional. The committee decided to allow 2.0 to come to the board for standardization. Mentor Graphics voiced concerns, but the standardization continued with the approval of Mentor Graphics.
b- OVI Verilog 1.0 followed the same process and despite many technical obstacles, it was approved by the board. In fact, OVI Verilog 1.0 was more of a user guideline than an LRM in today's standard. That is why OVI sold copies of Verilog-XL so that companies used the simulator as the standard instead of OVI 1.0 They also copied the same mistakes.
c- SDF followed the same process.
d- The same as others.
Cadence proposal is suggesting that Accellera Board stop "trusting" the judgement of the Verilog++ committee and transfer the technical judgement to the Accellera board. Cadence Verilog++ technical member has voted yes to make 3.0 as the standard. I am extremely amazed, on why Grant questions even his Cadence member's vote at the technical level. If we wanted to follow a rigorous process, we should have made SystemVerilog an IEEE committee from day one. OVI and I hope Accellera has made its marks in the industry on how efficient it can make standards. With the all imperfect standards that we generated in the last 12 years, no one has accused Accellera for delivering bad standards.
There is no argument on my side that more time will lead to better standards. This is exactly what we are doing. The plan is to do standards in stages. This has been the operating mode of OVI and I hope now with Accellera. The first stage is SystemVerilog 3.0, our second stage is 3.1 and the final stage is the support of IEEE standardization and Mac as the IEEE chairman for Verilog. This plan is intended to encourage tool developers to start building prototypes and help make 3.1 an implementable and usable standard so that IEEE committee can see a greater value in doing such a standard.
Any delay, no matter how simple it is, it will put us back at minimum of three months. Every issue, has to be debated, the we to develop proposals, debate this proposal, adjust the LRM and BNF (bigger problem), and then vote. Refine the LRM and then vote again on the full LRM. Believe me, at this point in the future, we will discover more issues. Then what?
Who will decide enough is enough? If the Accellera Board Does not Trust the current committee work, then how the Accellera Board will trust this committee's work (or any other) in the future?
This is pure delay tactics by the Cadence Board Representative. Changing the process that we started and approved as an Accellera Board, does not make sense at this final stages of SystemVerilog 3.0. Cadence had early copies before we started the formal process (prior to draft one). The newly discovered experts should have joined three months ago, when starting Draft One. They could have joined two months ago. They could have joined in the last meeting.
SystemVerilog 3.0 is the best we can deliver. More eyes can help, but also more cooks can also destroy the meal. We have the best experts in the industry in this committee. We have Phil Moorby (Verilog inventor), We have Peter Flake (Hilo inventor), we have the best developers of the best Verilog simulator (Mac and John), we have the best assertions experts in the industry, we have the best Verilog consultants (Cliff and Stu and two additional ones), we have one of the original developers for behavioral synthesis, we have three wonderful and popular simulator companies (ModelTech, Fintronics, and Silos-Verilog), We have Cadence expert (Paul) from Cadence synthesis group, and few more who joined later.
SystemVerilog is based on a real product that many designers use. It has gone through at least three years of development and enhancements.
Every committee that reports to me takes its job very seriously. Like other committees, Verilog++ has worked very hard, we have analyzed, we have debated and we have decided for SystemVerilog 3.0 as the standard. Any technical questioning in the Accellera Board is mistrust to this committee and its leaders. Any questions on approved staged standardization is misunderstanding to the Accellera standardization process which has proved very successful in the industry. If Cadence new experts, want to make SystemVerilog a better standard, they should have joined much earlier. In fact, they have every chance by making 3.1 a better standard. The opportunity for many Cadence to support this effort is available. Accellera practice and encourage tool prototyping for better standard.
Dennis and Mac have made their leadership's position known to the current and existing process. If you want to change such a process, please do not do it on the expense
of SystemVerilog 3.0. The committee has delivered the best standard it can provide with ALL current known issues. This is our technical decision. We have made the best decision with all known facts.
Now it is in your hands to accept it or reject it for any reason you want to construct.
My committee has done the best job. If anyone wants to debate its judgement, please do so in the committee, not in the board. The committee should be trusted to provide its best work with its current staff. My motto is join the committee early and work through the committee to make a better standard.
Thank you for trusting my committees.
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
Site Map: http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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