Subject: Agenda for May 20 Meeting
From: Vassilios.Gerousis@Infineon.Com
Date: Sun May 19 2002 - 08:39:25 PDT
Hello,
The agenda for May 20 meeting is:
1- Introduction.
2- SystemVerilog 3.0:
a- Cleanup issues (typos, clarification, etc.).
b- Target June 3 for Accellera Standard Release 3.0.
c- May 30 is final input to the LRM. If Stu approves this milestone.
d- Voting by Accellera Board on June 3.
3- Accellera membership meeting Wednesday at DAC.
4- Addition to 3.1 List.
5- Agenda for June 5 meeting in San Jose. This is will be a one day meeting with
assertion sister group. We will plan 3.1 release of both SystemVerilog and Assertions.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
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