Subject: RE: SystemVerilog LRM and Accellera Board Voting - A Suggestion f or moving forward
From: Michael McNamara (mac@verisity.com)
Date: Sat May 18 2002 - 10:29:47 PDT
As the chair of the IEEE 1364 Verilog Hardware Description Language
Working Group, as a member of Accellera's System Verilog committee,
and as a Member of Accellera Board of Directors, I endorse bringing
SystemVerilog 3.0 to the Accellera Board for a vote for acceptance as
an Accellera Standard, and I recommend that my fellow board members
vote in FAVOR of the proposal.
First, one must recognize that Verilog is owned by the IEEE; and is
not owned by Accellera. It is the case that Accellera (as OVI) is the
birth place of Verilog as a standard.
Recognizing that Accellera could play a very useful role as a
development crucible for Verilog, without the requirement to operate
according to the IEEE strictures and timelines, our Technical Chair
chose a year ago to seek donations of technology, and to form a
committee to develop these donations into a worthwhile set of
extensions to the language, with a goal of then proposing this set to
the IEEE-1364 WG when that group was ready.
Perhaps the only error here is that the Technical Committee chair
somehow failed to make perfectly clear to Grant the complete timeline;
as from the proper perspective Grant's observation that 3.0 isn't
complete and is not ready to go to the IEEE is fully accurate and is
totally consistant with the TCC's road map:
1) Accept the donation of technology, and develop it to a standard
that is at 90% of 'perfection' as a key milestone. (Accellera is
the beneficiary of donations from Verplex and from CoDesign for
this effort).
2) Stop at that point and bring this material from the committee to
the the board for ratification as a 'dot zero' version, so that
member companies may begin experimental implementation of this
'construction of committee'.
3) Based on the experience gained therefrom, develop the remaining
10%, while at the same time fixing those oversights discovered from
the real world experience Accellera member companies gain from
implementing the 3.0 standard.
This 3.1 standard, a fusion of the committee's work on the donated
technology as encompassed in SystemVerilog 3.0; together with the
experience gained from the developers of the existing half dozen
implementations of 1364-2001 as they implement 3.0, will make for a
very strong proposal for the IEEE 1364 working group to consider when
we reconvene this fall, and consider future development.
So, I choose to read Grant's proposal as that he is committing to
assign Stuart Swan and Steve Sharp to prototype an implementation of
SystemVerilog 3.0 in a branch of NC Verilog, and that they will
participate on the System Verilog committee by sharing the experience
gained from this, to the mutual benefit of all so that we can have the
best possible IEEE standard.
I, for one, welcome the assistance.
-- Michael McNamara Vice Chairman of Accellera IEEE-1364 Chairman Senior Vice President of Technology of Verisity
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