Subject: FW: SystemVerilog LRM and Accellera Board Voting - A Suggestion f or moving forward
From: Vassilios.Gerousis@Infineon.Com
Date: Sat May 18 2002 - 03:09:53 PDT
FYI.
We will proceed with our meeting next week as have been planned. If Cadence wants to vote against SystemVerilog at the board level, they have the opportunity. I do not plan to disturb our meeting next week with such discussions. If any of you believe this is a killing item for SystemVerilog 3.0, please let me know.
Either Paul or Erich are welcome to provide technical proposals to address Grant Martin's issues. You are also welcome to provide detailed explanation of any of these items brought by Cadence, is a show stopper. This needs to be done through emails. You also need to provide an explanation why, if any of them are new (especially Paul) why when we discussed the issue list these were not brought up?
Erich I am not ready to discuss Sugar versus SystemVerilog. We will do that at our meeting in San Jose planned for June 5.
Vassilios
-----Original Message-----
From: Vassilios.Gerousis@infineon.com
[mailto:Vassilios.Gerousis@infineon.com]
Sent: Saturday, May 18, 2002 11:49 AM
To: gmartin@cadence.com; accellera_bod@accellera.org
Subject: RE: SystemVerilog LRM and Accellera Board Voting - A Suggestion
f or moving forward
Importance: High
Hello Grant,
Thank you for providing your feedback.
Several of these have been discussed and they were delayed to SystemVerilog 3.1. The committee as a whole have discussed these over the last three months.
I am not going to delay SystemVerilog 3.0. I have followed very agonizing and rigorous process which Cadence representative was part of this and he voted to accept this document AS IS and forward this to the Accellera Board for Approval. Our Accellera Process Does Not Allow members to joint the last meeting and just bringing the "question" That Verilog Syntax should be changed to Sugar. Sugar has been accepted as the basis for formal specification, but in it is in no shape or form of a standard. Since no commercial tools exist yet, it is better for Sugar to be changed and not the other way around.
Cadence has been proactive in this effort over the last 4 months. We have identified a list of issues to solve for 3.0 and we have voted on some of them to be postponed for 3.1. Cadence representative was present in many of those discussions and voting. At HDLCON, we have put a plan for listing all issues that all members, including Cadence brought to the committee. In the last two months, we have scheduled all issues and discussed them, one by one and have worked hard every week to provide acceptable closure to all items that was brought to the committee.
This is extremely puzzling for me right now. The Cadence representative has been very cooperative and very responsive in providing changes and helping in making this 3.0 a VERY GOOD AND EXCELLENT work. By the fact that he voted to accept this to be passed to the Accellera board, shows that he has accepted its content. He is also aware of the issues that you presented and he is also part of the team who voted to postponed things to 3.1. The reason we have scheduled 3.1 is to clean the document and obtain feedback of current EDA vendors who are building prototypes.
Any expert can tell you that IEEE 2001 have additional complexity to the compilation process. Adding SystemVerilog, the complexity increases and the compilation will increase. The donors of this wonderful technology are the real experts who in the first place invented Verilog. They have considered every possible way to easy the compilation complexity.
None of the items you have brought up are a show stopper. We can spend the next five years trying to make this more sound. In my humble opinion, you need to implement a prototype and then come back with practical feedback. We all have opinions, and until you start building a prototype, more discussions will not make the standard more sounds.
I believe it is a year too late to question the scope of SystemVerilog. This committee was established with the vote of every Accellera board member including Cadence. The scope of both SystemVerilog and Assertions were presented and given every chance to all members (Board and technical committee members). The scope, deliverables of SystemVerilog and assertions were developed the technical committee of 15 people, one year ago. They were documented and they were also discussed in many meetings. We have attracted almost 10 small EDA companies that worked hard and provided excellent technologies which today we call SystemVerilog 3.0.
In my many years of history of standards (more than 10 years). This is the best LRM that OVI/Accellera have put together. Verilog-AMS 2.0 has problems, but we pass them through. Towards the end of any standard, the committee will always struggle in identifying what should be in and what should be postponed. To do this properly, the members need to participate. The earlier you participate, the earlier that you can help to make the standard better. SystemVerilog committee is made of industry experts including the original authors of Verilog and Hilo. By the mere fact of your proposal to delay the standard, you are saying to those experts, including Cadence representatives (PAUL GRAHAM) that their work in the last year is not sound. In addition, their vote is not worth a penny.
I am extremely offended by such behavior as a technical chair of Verilog++. As I mentioned above, these will be discussed and considered in SystemVerilog 3.1. This is how the committee of experts have agreed and voted.
Thanks
Vassilios
-----Original Message-----
From: Grant Martin [mailto:gmartin@cadence.com]
Sent: Friday, May 17, 2002 6:31 PM
To: Vassilios.Gerousis@infineon.com; accellera_bod@accellera.org
Subject: Re: SystemVerilog LRM and Accellera Board Voting - A Suggestion
for moving forward
Vassilios
First, let me say that the document (draft 8) on SystemVerilog that was
sent out May 3 clearly reflects a lot of excellent work and I would like to
congratulate the Verilog++ (HDL+) committee on this, and the assertions
committee as well, for all their hard work.
I have circulated the document to several technical experts in Cadence, and
they have been sending feedback both to me and into the committee via our
current representatives, Paul Graham and Erich Marschner. I understand
there has been a productive dialogue around feedback from several committee
members.
We have some concerns that a wee bit more work is required by the Verilog++
committee before the standard is ready to be voted on by the Accellera
board. This additional work would be to resolve the various technical
issues raised. There is also some concern about the scope of
SystemVerilog 3.0 as well.
Specific issues raised include:
a. Deferred definition of types.
b. Deferred definition of interfaces.
c. Based on a, and b, the issue of independent compilation of Verilog,
which is a growing issue as systems and their models grow larger.
c. Virtual interfaces and their complexity.
d. Assertion statement definition- syntactic and semantic conflicts between
the System Verilog assertion statements and the Accellera standard property
language (Sugar) forms of assertion.
I understand that several Verilog++ committee members, and reviewers, from
Cadence, LSI Logic, National Semiconductor, and Verplex, among others, have
been discussing them via the committee's email reflector.
It is of course in the interests of all Accellera members and non-members,
and especially users, that any new approved standard be as technically
sound as possible. It also seems that resolution of issues may not require
a large amount of time, by the Verilog++ committee.
It would be unreasonable of me to suggest that the committee spend more
time on the SystemVerilog draft standard without also finding additional
ways to help the committee. I have been able to identify 2 Verilog experts
from Cadence Systems and Functional Verification, Steve Sharp and Stuart
Swan, who also have much experience with standards work, who would be able
to join the SystemVerilog committee and help in resolution of any issues
with the current draft. I hope the committee would be able to make use of
their expertise.
Therefore, I would like to suggest that rather than vote by June 3 to
accept the proposed draft standard, that instead the Verilog++ committee
take the additional time needed to resolve these issues and others that may
have come up in the course of review, and then submit a further revision
for approval after resolving the issues, at a later date when the committee
feels it is ready. I would also like to offer the help of Steve Sharp and
Stuart Swan to the committee to help in such resolution. And I would like
to encourage others to also offer additional help to the committee if possible.
What do people think? Comments and discussion very welcome.
Best Regards and Thanks again to the committee for all its past, present
and future work
Grant Martin
At 11:01 AM 5/3/2002 +0200, Vassilios.Gerousis@infineon.com wrote:
>I am pleased to announce that after one year of hard work on behalf of the
>Verilog++ committee and also the assertion committee, we now have a
>proposed standard ready for the Accellera Board approval.
>Enclosed you will find latest draft (draft 8) which was voted by the
>Verilog++ committee on Monday, April 29 with a 99% majority in favor for
>standardization. Based on the traditional voting rules, the board members
>now have one month to review and vote for approval of the LRM for
>standardization by the latest June 3rd. In the meantime, the committee
>will be spending
>time to clean the document (wording mistakes, clarification, and any
>cosmetic changes).
>1- Please send the document to your experts within your companies. Any
>feedback should be send to me and I will forward this to the committee.
>2- Please target June 3rd or earlier for your voting approval by email.
>3- Georgia, will start a press release from Accellera to announce
>SystemVerilog LRM standard and its support from the board and key
>individuals of the Verilog++ committee.
>
>Best Regards
>
>Vassilios
> <<SystemVerilog_draft8.pdf>>
>
>
>------------------------------------------------------------------------------------------------------------------------------
>Dr. Vassilios Gerousis Infineon Technologies
> DAT CAD, MchB
>Telephone: +49-89-234-21342 BalanSt. 73
>Fax: +49-89-234-23650 D-81541 Munich
>email: Vassilios.Gerousis@infineon.com Germany
>Site Map:
>http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
>----------------------------------------------------------------------------------------------------------------------------------
>
------------------------------------------------------------------------------------------------------
Grant Martin
Fellow, Cadence Labs tel. +1-510-647-2804
Cadence Design Systems mobile +1-510-703-7470
2001 Addison Street, Third Floor fax. +1-510-486-0205
Berkeley, California 94704 U.S.A. email gmartin@cadence.com
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