Subject: Re: Poll of the Week - www.eedesign.com
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Apr 18 2002 - 07:34:11 PDT
Hi Dennis
I'm surprised! OVL isn't part of the list. I guess only take
the most recently discussed elements and take a poll.
It's funny that they separate 1 & 2. The assertion language is supposed
to allow simple Accelera formal language sequences. So if you pick #1
you get part of #2.
I'd pick the one that supports:
o access to previous (in time) signal values.
o can be embedded directly into verilog modules.
o supports overlapped assertions without additional verilog modeling.
I don't know if the choices support all of these.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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