Subject: Re: BNF question
From: Shalom.Bresticker@motorola.com
Date: Thu Apr 18 2002 - 00:42:07 PDT
I don't think that is the reason Verilog does not allow it.
Verilog allows a lot of stuff which does not correspond to real hardware.
I guess NC-Verilog does not allow it simply because the standard does not allow
it, as Mac has pointed out.
(By the way, Mac, congratulations on your election to 1364 chair.
If you come to Israel to visit your Israeli branch of Verisity,
then ring up a telephone while you're here.)
We might be able to find the real reason in the archives, if we looked hard
enough.
Shalom
On Wed, 17 Apr 2002, Paul Graham wrote:
> > I imagine it was made illegal because it makes the length of the expression
> > uncomputable at compilation time.
> >
> > It might not be so bad in Verilog-XL, which is semi-interpreted, but in a
> > code compiler, such as NC, it is probably a problem.
>
> NC-VHDL handles constructs whose length is uncomputable at compilation time
> (variable-length slices and aggregates). Since NC-VHDL is also a native
> code compiled simulator, there must be another reason. Probably the same
> reason that verilog disallows all other variable-length constructs -- they
> don't correspond to real hardware.
-- Shalom Bresticker Shalom.Bresticker@motorola.com Principal Staff Engineer Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
This archive was generated by hypermail 2b28 : Thu Apr 18 2002 - 00:53:21 PDT