Subject: Re: BNF question
From: Paul Graham (pgraham@cadence.com)
Date: Wed Apr 17 2002 - 10:18:55 PDT
> I imagine it was made illegal because it makes the length of the expression
> uncomputable at compilation time.
>
> It might not be so bad in Verilog-XL, which is semi-interpreted, but in a
> code compiler, such as NC, it is probably a problem.
NC-VHDL handles constructs whose length is uncomputable at compilation time
(variable-length slices and aggregates). Since NC-VHDL is also a native
code compiled simulator, there must be another reason. Probably the same
reason that verilog disallows all other variable-length constructs -- they
don't correspond to real hardware.
Paul
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