RE: June 5 HDL+ Committee Meeting At Synopsys Building B Mountain View

Subject: RE: June 5 HDL+ Committee Meeting At Synopsys Building B Mountain View
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Jun 04 2002 - 08:06:48 PDT

http://www.synopsys.com/cgi-bin/mapquest/mqcustomconnect?streetaddress=700+East+Middlefield+Rd&city=Mountain+View&state=CA&zip=94043

The map is above.

The address

700 East Middlefield Rd Mountain View CA 94043

-----Original Message-----
From: Harry Foster [mailto:harry@verplex.com]
Sent: Tuesday, June 04, 2002 10:21 AM
To: Vassilios.Gerousis@Infineon.Com; vlog-pp@eda.org; assertion@eda.org;
gmartin@cadence.com
Subject: RE: June 5 HDL+ Committee Meeting At Synopsys Building B
Mountain View

Hi Vassilios,

Do you happened to know the exact address for the Synopsys
Building B location--for us "Bay Area Challenged" folk?
This way I can look it up on Mapquest to figure out how to
get there.

Best regards,

-Harry
---------------------------------------------------------
Harry Foster Tel 972-423-3186
Chief Architect Cell 408-464-6406
Verplex Systems, Inc. mailto:harry@verplex.com
300 Montague Expwy, Suite 100 www.verplex.com
Milpitas, CA 95035 www.verifiableRTL.com

> -----Original Message-----
> From: owner-assertion@eda.org [mailto:owner-assertion@eda.org]On Behalf
> Of Vassilios.Gerousis@Infineon.Com
> Sent: Friday, May 31, 2002 12:58 AM
> To: vlog-pp@eda.org; assertion@eda.org; gmartin@cadence.com
> Subject: June 5 HDL+ Committee Meeting At Synopsys Building B Mountain
> View
>
>
>
> > Hello Dear Verilog++ and Assertions committees members,
> > Synopsys has agreed to host our meeting and also to host
> our teleconference for June 5th, 2002. Here are details
> >
> > 1- Place: Synopsys (Mountain View) - Building B in the Amethyst
> conference room.
> > 2- Time: 9:00 AM - 4 PM.
> > 3- Date: June 5, 2002.
> > 4- Teleconference Information are:
> > International participants: 734-414-0268
> > Domestic participants: 877-300-8186
> > Participant code: 810623
> >
> > Agenda:
> >
> > 1- Introduction --- 9:00 - 9:30 AM.
> > 2- List of the Accellera SystemVerilog Committee Issues
> (Assertion+Verilog+) that the committee has put together for the
> last year.
> > 3- List Of Issues Generated By Accellera Board Members:
> > a- Cadence.
> > 4- Assertions (OVL) Plans -- 10:00 - 10:30. -- David Lacey
> > 5- SystemVerilog 3.1 Plans -- 10:30 - 11:00.
> > 6- Proposed enhancements and related proposals: two hours.
> > a) Testbench features
> > b) Unified Assertions will start at 2:00 pm
> > c) C interface
> > d) Extended API
> 7- Planning, milestone development, scheduling 3.1, etc. 3:00 PM - 4:00 PM
>
> > Time may change based on breaks, lunches, etc.
> >
> > Best Regards
> >
> > Vassilios
> >
> >
> ------------------------------------------------------------------
> ------------------------------------------------------------
> > Dr. Vassilios Gerousis Infineon Technologies
> > DAT CAD, MchB
> > Telephone: +49-89-234-21342 BalanSt. 73
> > Fax: +49-89-234-23650 D-81541 Munich
> > email: Vassilios.Gerousis@infineon.com Germany
> > Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> --------------------------------------------------------------------------
--------------------------------------------------------
>
>

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