Subject: Re: Proposal: Implicit Port Instantiation in SystemVerilog
From: Alec Stanculescu (alec@fintronic.com)
Date: Mon Dec 17 2001 - 09:43:46 PST
I agree with Kris that the .* will greatly improve both writeability
and readability. The semantics should be those of inherit/export as Kevin
suggested. However, do we really need the additional inherit/export
keywords?
Perhaps just writing the rules for inheritance (precisely how the
signals should be searched in the parent scope(s)) may be sufficient.
Or, perhaps the inherit/export may only be necessary for the Vss/Vdd
signals to be searched in subscopes of the parent, but not the regular
signals which must be found (or else an error shall be reported) only
in the scope of where the module is instantiated. So, we could have
different rules for signals declared with inherit/export than for the
others.
The combination of both port association by name and .* seems the most
attractive to me.
Alec
> Sender: owner-vlog-pp@eda.org
> Precedence: bulk
>
> I think your perspective on this comes much from
> your application domain. In microprocessor design, we
> have a large number of leaf blocks (with cells and
> macro blocks instantiated with "traditional" connectivity).
> Above that, the hierarchies are created for logical
> verification purposes with the occasional multiple
> instantiations. These hierarchies also assist in
> encapsulation logic to reduce the debug complexity
> of large models. But, for the most part, the signals
> are not redundant, and the expectation is that
> above that "leaf" level, signals are all unique.
>
> It is not uncommon to see blocks with hundreds to
> thousands of signals (not vector expanded!). Today, we
> create these lists and instantiations through a
> generation program vs. typing the signal in at
> those levels. The .* will allow large block
> instantiation without the pain of creating large,
> redundant signal lists.
>
> Thanks,
> KRis
>
> -----Original Message-----
> From: Kevin Cameron x3251 [mailto:dkc@galaxy.nsc.com]
> Sent: Friday, December 14, 2001 2:07 PM
> To: vlog-pp@eda.org
> Cc: Kris@ichips.intel.com; mmaidmen@ichips.intel.com
> Subject: Re: Proposal: Implicit Port Instantiation in SystemVerilog
>
>
>
> Apart from reducing keystrokes, I'm not sure what problem this solves.
> Typing mechanisms in Verilog seem lax enough to me as it is. Why add
> another opportunity to make non-obvious errors?
>
> Having said that, you could consider including a solution for the
> Verilog-AMS problem of how to wire up power & ground for analog modules
> in mixed design hierarchies, and "kill two birds with one stone".
>
> Specifically; the problem in Verilog-AMS is that A/D conversion modules
> need to connect into the nearest Vss/Vdd to get accurate results, but don't
> know where in the parent hierarchy those signals are declared.
> Personally I would go for something an "inherit <signal>" declaration
> in the child module, and maybe a matching "export <signal>" in the parent
> - but I'm open to suggestions.
>
> Regards,
> Kev.
>
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