Subject: RE: Proposal: Implicit Port Instantiation in SystemVerilog
From: Konigsfeld, Kris (kris.konigsfeld@intel.com)
Date: Mon Dec 17 2001 - 08:20:45 PST
I think your perspective on this comes much from
your application domain. In microprocessor design, we
have a large number of leaf blocks (with cells and
macro blocks instantiated with "traditional" connectivity).
Above that, the hierarchies are created for logical
verification purposes with the occasional multiple
instantiations. These hierarchies also assist in
encapsulation logic to reduce the debug complexity
of large models. But, for the most part, the signals
are not redundant, and the expectation is that
above that "leaf" level, signals are all unique.
It is not uncommon to see blocks with hundreds to
thousands of signals (not vector expanded!). Today, we
create these lists and instantiations through a
generation program vs. typing the signal in at
those levels. The .* will allow large block
instantiation without the pain of creating large,
redundant signal lists.
Thanks,
KRis
-----Original Message-----
From: Kevin Cameron x3251 [mailto:dkc@galaxy.nsc.com]
Sent: Friday, December 14, 2001 2:07 PM
To: vlog-pp@eda.org
Cc: Kris@ichips.intel.com; mmaidmen@ichips.intel.com
Subject: Re: Proposal: Implicit Port Instantiation in SystemVerilog
Apart from reducing keystrokes, I'm not sure what problem this solves.
Typing mechanisms in Verilog seem lax enough to me as it is. Why add
another opportunity to make non-obvious errors?
Having said that, you could consider including a solution for the
Verilog-AMS problem of how to wire up power & ground for analog modules
in mixed design hierarchies, and "kill two birds with one stone".
Specifically; the problem in Verilog-AMS is that A/D conversion modules
need to connect into the nearest Vss/Vdd to get accurate results, but don't
know where in the parent hierarchy those signals are declared.
Personally I would go for something an "inherit <signal>" declaration
in the child module, and maybe a matching "export <signal>" in the parent
- but I'm open to suggestions.
Regards,
Kev.
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