Subject: Proposal: Implicit Port Instantiation in SystemVerilog
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Dec 13 2001 - 16:07:31 PST
Hi, All -
Attached is a proposal for adding implicit port declarations to
SystemVerilog. This can serve as a starting point for our next discussion
on the topic. I have copied Kris Konigsfeld and Matt Maidment of Intel,
Oregon, in case they would like to comment on the proposal, since they
contributed significantly to the concept of this proposal.
Apologies for the delay, it took a while to come up with and interesting
example and full explanation of the intended enhancement.
Comments?
Regards - Cliff
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