Subject: Re: Proposal: Implicit Port Instantiation in SystemVerilog
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Dec 14 2001 - 09:02:18 PST
Good morning Cliff;
This is a capability that I have seen in some for at 3 companies now.
Each company had varying improvements over this basic concept.
In fact there is a tool called Mktree that implements this concept.
I would like to point out several places where this concept can
(should?) be extended to facilitate greater usefulness, especially
for large systems (SystemVerilog.)
1. One needs to compare this capability with the interface capabilities.
The example interfaces look okay, but I have not seen more complex
examples where not all the ports are required, ports are driven
from multiple blocks instead of just one, etc.
2. This does not work when two instantiations of the same block
are needed. Consider the example of instantiating two accumulators.
module accumulator (
input clk, rst_n,
output [31:0] acc,
input [31:0] alu_out,
input ld_acc
);
You could not instantiate two accumulators without having their
nets shorted together, since they have the same name.
The Bening/Foster paper on Implicit connections used regular
expressions to enable production of new net names based on the
original port name and a combination of prefixes, suffixes to
the net name.
Then the use of regular expressions also allows selection of port
names to place particular rules on multiple sets of ports.
3. Even with this capability, with multiple levels of hierarchy, one
still needs to modify the ports of modules above the leaf nodes,
when adding new signals. A tool I have been working on and
another I have seen would effectively build the intermediate
hierarchy modules port lists. This would allow a system developer
to group components in a level of hierarchy without regard to
port names/connections unless specific changes needed to be
applied. The tool would then determine what modules across the
full heirarchy needed to be connected together and the module
ports and connections made.
This capability then made adding/removing signals a very fast
process, because one did not have to check out several modules
in the hierarchy between the two modules. It was particularly
more effective because it allowed two people to add/remove ports
and not become entangled in each others changes.
I do like this capability, I wanted others to appreciate the
helpfulness of it, but also the new set of problems that shows
up.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Fri Dec 14 2001 - 09:02:57 PST