Subject: Re: Proposal: Implicit Port Instantiation in SystemVerilog
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Fri Dec 14 2001 - 14:06:59 PST
Apart from reducing keystrokes, I'm not sure what problem this solves.
Typing mechanisms in Verilog seem lax enough to me as it is. Why add
another opportunity to make non-obvious errors?
Having said that, you could consider including a solution for the
Verilog-AMS problem of how to wire up power & ground for analog modules
in mixed design hierarchies, and "kill two birds with one stone".
Specifically; the problem in Verilog-AMS is that A/D conversion modules
need to connect into the nearest Vss/Vdd to get accurate results, but don't
know where in the parent hierarchy those signals are declared.
Personally I would go for something an "inherit <signal>" declaration
in the child module, and maybe a matching "export <signal>" in the parent
- but I'm open to suggestions.
Regards,
Kev.
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