Subject: Re: Proposal for array types
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Mon Apr 08 2002 - 10:16:49 PDT
> From: "Paul Graham" <pgraham@cadence.com>
>
> Here is my proposal for array types in SystemVerilog 3.0. I'm referencing
> the draft 5 manual. The intent of this proposal is to implement these
> points from my recent e-mail:
>
> 3. Allow reading and writing of whole arrays.
>
> 4. Allow slicing of one-dimensional arrays (for both reading and writing).
>
> 5. Allow general array ports of subprograms and modules.
>
> 6. Provide functions or attributes to get the bounds of a dimension of an
> array. I would suggest new system functions like $left, $right, etc.,
> corresponding to VHDL attributes for querying array bounds.
>
> Here goes ...
.....
> Section 16 System tasks and system functions
>
> 16.1 Introduction
>
> Change:
>
> SystemVerilog adds a system function to determine the bit size of a
> value.
>
> to:
>
> SystemVerilog adds several system function to determine the bit size of
> a value and the bounds of an array.
>
> Add:
>
> 16.3 Array querying functions
>
> Five new system functions are provided to return the bounds of an
> array. Each function has the syntax:
>
> <function>(<array>, <dimension>)
>
> where <function> is one of {$left, $right, $low, $high, $size}. <array>
> is any declared array. <dimension> specifies which dimension of the
> array is to be queried.
>
...
I suggest dropping $low and $high, and adding $increment - which will return
-1,0 or 1 for the right -> left increment. A non-existant dimension would
return 0,-1,1 for $left, $right, $increment. A zero value for $increment
indicates a single element array or a scalar.
$increment would be forward compatible if we allow increments other than
1 (or the array is foreign).
Kev.
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