Subject: Re: Clean up items to sections 8 and 10
From: Peter Flake (flake@co-design.com)
Date: Mon Apr 01 2002 - 06:54:22 PST
Stu,
I agree with most of your changes. I have one comment.
At 01:35 PM 3/28/02 -0800, Stuart Sutherland wrote:
>5. Draft 4, Section 8.3, Selection assignments:
>The first paragraph does not explain how SystemVerilog differs from
>Verilog. I suggest the sentence be changed from:
> "The condition is evaluated as a boolean so that 0 or X or
> null or void or {} are false and any other values are true."
>To:
> "In Verilog, an 'if (expression)' is evaluated as a boolean,
> so that if the result of the expression is 0 or X, the test
> is considered false. With SystemVerilog, null or void or {}
> are also false."
I suggest deletion of null and {} since SystemVerilog does not have any
data types which can take those values.
Peter.
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