Subject: Re: Fwd: datapath enhancements to verilog
From: Michael McNamara (mac@verisity.com)
Date: Mon Dec 10 2001 - 14:02:42 PST
Paul Graham writes [deleted VHDL comparisons --mac]:
> For instance, it is possible to declare a deferred port in Verilog-DP of an
> array type whose bit size is unspecified:
>
> module m(q, d1, d2);
> output [] q;
> input [] d1[], d2[];
> assign q = d1 + d2;
> endmodule
>
> Suppose you want to use module m above to add 8-bit words and also 16-bit
> words. It's easy in Verilog-DP:
>
> wire [7:0] q8, d8_1 [3:0], d8_2[3:0];
> wire [15:0] q16, d16_1 [3:0], d16_2[3:0];
>
> m u8(q8, d8_1, d8_2);
> m u16(q16, d16_1, d16_2);
>
> Paul
To continue the thought experiment, in Verilog 2001, one could
(almost: Verilog 2001 doesn't allow operations like '+' on arrays)
code module m as:
module m #(wq = 1, wd1 = 1, dd1 = 1, wd2 = 1, dd2 = 1)
( output [wq-1:0] q,
input [wd1-1:0] d1 [dd1-1:0],
input [wd2-1:0] d2 [dd1-1:0]);
assign q = d1 + d2;
endmodule
and then instantiate as:
parameter wq8 = 8, dq8 = 4;
parameter wq16 = 16, dq16 = 4;
wire [wq8-1:0] q8, d8_1 [dq8-1:0], d8_2[dq8-1:0];
wire [wq16-1:0] q16, d16_1 [dq16-1:0], d16_2[dq16:0];
m #(wq=wq8, wd1=wq8, dd1=dq8, wd2=wq8, dd2=dq8) u8(q8, d8_1, d8_2);
m #(wq=wq16, wd1=wq16, dd1=dq16, wd2=wq8, dd2=dq16) u16(q16, d16_1, d16_2);
This does end up with a lot of repetitive typing, and chances to omit
a parameter override.
-mac
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