Subject: Re: Fwd: datapath enhancements to verilog
From: Paul Graham (pgraham@cadence.com)
Date: Mon Dec 10 2001 - 13:23:55 PST
> IMO if VHDL is already doing this stuff then we should work on
> language interoperability rather than trying to do it again with different
> syntax.
Kevin,
Good to hear from you. I've become less of a VHDL bigot these days :-)
It's true that many Verilog-DP (and Verilog-2001) features are closely based
on VHDL features. But Verilog-DP does some things which are very awkward
to emulate in VHDL.
For instance, it is possible to declare a deferred port in Verilog-DP of an
array type whose bit size is unspecified:
module m(q, d1, d2);
output [] q;
input [] d1[], d2[];
assign q = d1 + d2;
endmodule
As you know, it is impossible in VHDL to declare an array type whose element
type is an unconstrained array. You could declare an array type whose
element type is an array constrained by a generic, but you could declare it
such that it could be used in a port declaration.
Suppose you want to use module m above to add 8-bit words and also 16-bit
words. It's easy in Verilog-DP:
wire [7:0] q8, d8_1 [3:0], d8_2[3:0];
wire [15:0] q16, d16_1 [3:0], d16_2[3:0];
m u8(q8, d8_1, d8_2);
m u16(q16, d16_1, d16_2);
In VHDL you would have to declare separate types with 8- and 16-bit words,
and declare separate entities which differ only in types used. Things get
really messy if you want to add an array of 8-bit words to an array of
16-bit words.
Likewise, it is possible to defer the sign type of a port in Verilog-DP. In
VHDL you would have to declare separate types for signed and unsigned.
Unfortunately, VHDL took Ada's strong generic package concept and watered
it down to the level of Verilog parameters.
Paul
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