Subject: Re: Fwd: datapath enhancements to verilog
From: Kevin Cameron (dkc@galaxy.nsc.com)
Date: Mon Dec 10 2001 - 13:12:58 PST
Stuart Sutherland wrote:
> Vassilios,
>
> Could we add discussion the following to the agenda for Jan 7? The
> discussion should be limited to whether or not to pursue this for
> SystemVerilog 3.0.
>
> Stu
IMO if VHDL is already doing this stuff then we should work on
language interoperability rather than trying to do it again with different
syntax.
Regards,
Kev.
PS: It would be helpful to have an equivalent of the VHDL "'" used
for implicit signals etc., and I was wondering if ".$" would work or
would it clash with other syntax - e.g.:
<object path>.$<implicit>
always (@ clock) begin
if (top.block.0.data.$last) // if true before....
PPS: This is not a request to add it now.
> >From: Paul Graham <pgraham@cadence.com>
> >
> >
> >Cliff,
> >
> >At Cadence we are working on a set of extensions to Verilog to support
> >datapath designs. These extensions are based on the Verilog-2001 standard.
> >We call the extended language Verilog-DP. We would like these extensions to
> >be considered candidates for future versions of the Verilog standard.
> >
> >We have a nice user document under construction, but I can summarize the
> >language features. I'll give some examples at the end.
> >
> >The extensions fall into several categories:
> >
> >1. Extension of array functionality.
> >
> > a. Verilog-DP removes many of the restrictions on arrays that are present
> > in Verilog-2001. It allows reading and writing of whole arrays and
> > array slices, like VHDL. Modules and subprograms can have array
> > ports.
> >
> > b. New system functions like $size, $high, etc., are similar to VHDL
> > attributes 'LENGTH, 'HIGH, etc. These are convenient when dealing
> > with arrays and especially with deferred array ports (see below).
> >
> > c. Word concatenation. An array can be built up from individual words
> > using a word concatenation. A word concatenation is intended only for
> > initializaing an array (much like a C array initializer).
> >
> > d. Array unary and binary operations. Unary and binary operations
> > perform the equivalent word operation on each element of an array, or
> > between corresponding elements of two arrays. There are special
> > operations for matrix multiplication and inner product. There are
> > also reduction operators which combine elements of an array to produce
> > a word.
> >
> > e. System functions $flatten and $unflatten convert between an array type
> > and a flat bit-vector.
> >
> >2. Datapath-specific system functions.
> >
> > a. Certain primitive functions encountered frequently in datapath designs
> > are encapsulated as new system functions. For instance, there is a
> > saturation primitive $sat. As primitives, they can be recognized and
> > handled specially by a synthesis tool.
> >
> >3. Deferred declarations.
> >
> > a. The bounds of a module or subprogram port can be deferred (this is
> > similar to an unconstrained type in VHDL). The signedness of a port
> > can also be deferred. The bounds and sign are resolved based on the
> > arguments to the instantiation. Functions like $size and $is_signed
> > can be used to query the characteristics of a deferred port.
> >
> > b. Clone declarations. Similar to a deferred declaration, a clone
> > declaration allows a declared reg or wire to inherit the size and sign
> > of an existing declaration.
> >
> >
> >Examples:
> >
> > module m(q, d1);
> > output [] q; // deferred port
> > input signed [7:0] d1[7:0]; // array port
> > input signed [] d2[]; // deferred array port, deferred sign
> > input signed() [] d1[], d2[]; // deferred array ports, deferred
> > sign
> > ...
> > reg clone(d2) c;
> > reg signed($is_signed(d2)) [$left(d2,0):$right(d2,0)] c
> > [$left(d2,1):$right(d2,1)];
> > // The above two declarations of c are equivalent
> > ...
> > assign c = d2; // assign all of array d2 to c
> > assign c[3:0] = d2[7:4]; // assigning 4 words from d2 to c
> > ...
> > assign q = &d1; // q = d1[0] & d1[1] & ... & d1[7]
> > assign c = d1 + d2; // c[i] = d1[i] + d2[i] for each i
> > assign q = d1 * d2; // inner product
> > ...
> > wire [7:0] m1 [3:0][2:0];
> > wire [7:0] m2 [2:0][4:0];
> > wire [7:0] m3 [3:0][4:0] = m1 * m2; // matrix multiply
> > ...
> > wire [7:0] x [3:0] = [1, 2, 3, 4]; // word concatenation
> > wire [31:0] x2 = $flatten(x); // flatten into bits
> > wire [3:0] x3[7:0] = $unflatten(x2); // unflatten bits into array
> > ...
> > assign q = $lead0(d1[1]); // primitive to count leading zeros
> > ...
> >
> >
> >What do you think?
> >
> >Paul
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland Sutherland HDL Inc.
> stuart@sutherland-hdl.com 22805 SW 92nd Place
> phone: 503-692-0898 Tualatin, OR 97062
> www.sutherland-hdl.com
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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