Subject: Re: Fwd: datapath enhancements to verilog
From: Paul Graham (pgraham@cadence.com)
Date: Mon Dec 10 2001 - 14:17:36 PST
> To continue the thought experiment, in Verilog 2001, one could
> (almost: Verilog 2001 doesn't allow operations like '+' on arrays)
> code module m as:
>
> module m #(wq = 1, wd1 = 1, dd1 = 1, wd2 = 1, dd2 = 1)
> ( output [wq-1:0] q,
> input [wd1-1:0] d1 [dd1-1:0],
> input [wd2-1:0] d2 [dd1-1:0]);
>
You could, if only Verilog-2001 allowed array ports!
paul
This archive was generated by hypermail 2b28 : Mon Dec 10 2001 - 14:19:50 PST