Subject: Re: Another Sunburst Design FSM Example Design
From: Anders Nordstrom (asic@sympatico.ca)
Date: Fri Jan 11 2002 - 14:42:41 PST
Cliff,
Your examples in your document are not consistent with what you state below.
Your two always block FSM is not doing what your diagram is showing. If you
add the assignments to y1 in fsm2 it becomes as verbose as fsm1 and fsm3.
In your diagram you show that y1 = 0 in state S0, S1, S2, S4, S5, S6, S7
and S8
and y1 = 1 in S3 and S9. fsm1 can be condensed if you use the default
assignment
to y1 and only assign it to 1 in S3 and S9.
Regards,
Anders
Clifford E. Cummings wrote:
> Hi, All -
>
> Attached is another example of a state machine coded using a common
> Verilog-2001, one always block coding style (similar to the first
> SystemVerilog FSM coding style), followed by the first SystemVerilog
> FSM coding style (using a slightly modified syntax of enum_state and
> assuming that state encodings can be assigned - in the first version
> of this design, the encodings would probably be omitted and only added
> later if control over the state encodings is desired), and finally a
> Verilog-2001, two always block implementation.
>
> The outputs are Moore output assignments and I was not sure if the
> begin-end pair were required (example):
> S3 : if (jmp) begin
> y1 = 1'b1;
> ->> S3;
> end
> else ->> S4;
>
> or if a condensed assignment style could be made without begin-end
> (example?):
> // no if-statement to separate the ->> S3
> // and the assignment of y1 = 1'b1;
> S3 : if (jmp) ->> S3 y1 = 1'b1;
> else ->> S4;
>
>
>
> Note that in a state machine with multiple transition arcs to the same
> state, the output assignment has to be made for every transition arc
> to that state while using the two always block style only requires
> each output to be assigned once for each state.
>
> The more interconnected the state machine, the more verbose a one
> always block style becomes. Same is true for the SystemVerilog
> transition version. This is just one reason I typically discourage
> coding an FSM using only one sequential always block.
>
> This is why I don't think the SystemVerilog version is as concise as I
> originally thought.
>
> One could break a SystemVerilog FSM into two always blocks to remove
> the verbosity, but then we lose the @(posedge clk) syntax from the
> enumerated state declaration < "enum_state {...} state @(posedge
> clk)"> that allowed us to delete the 3-line sequential always block.
> Again no improvement in coding verbosity.
>
> For this type of state machine, the Verilog-2001, two always block
> style is much more concise than the enhanced SystemVerilog FSM style.
>
> More to come.
>
> Regards - Cliff
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