Subject: Another Sunburst Design FSM Example Design
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Tue Dec 11 2001 - 16:18:19 PST
Hi, All -
Attached is another example of a state machine coded using a common
Verilog-2001, one always block coding style (similar to the first
SystemVerilog FSM coding style), followed by the first SystemVerilog FSM
coding style (using a slightly modified syntax of enum_state and assuming
that state encodings can be assigned - in the first version of this design,
the encodings would probably be omitted and only added later if control
over the state encodings is desired), and finally a Verilog-2001, two
always block implementation.
The outputs are Moore output assignments and I was not sure if the
begin-end pair were required (example):
S3 : if (jmp) begin
y1 = 1'b1;
->> S3;
end
else ->> S4;
or if a condensed assignment style could be made without begin-end (example?):
// no if-statement to separate the ->> S3
// and the assignment of y1 = 1'b1;
S3 : if (jmp) ->> S3 y1 = 1'b1;
else ->> S4;
Note that in a state machine with multiple transition arcs to the same
state, the output assignment has to be made for every transition arc to
that state while using the two always block style only requires each output
to be assigned once for each state.
The more interconnected the state machine, the more verbose a one always
block style becomes. Same is true for the SystemVerilog transition version.
This is just one reason I typically discourage coding an FSM using only one
sequential always block.
This is why I don't think the SystemVerilog version is as concise as I
originally thought.
One could break a SystemVerilog FSM into two always blocks to remove the
verbosity, but then we lose the @(posedge clk) syntax from the enumerated
state declaration < "enum_state {...} state @(posedge clk)"> that allowed
us to delete the 3-line sequential always block. Again no improvement in
coding verbosity.
For this type of state machine, the Verilog-2001, two always block style is
much more concise than the enhanced SystemVerilog FSM style.
More to come.
Regards - Cliff
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