Subject: question about array port mismatches
From: Paul Graham (pgraham@cadence.com)
Date: Wed Jan 16 2002 - 10:37:32 PST
I didn't find the answer to this question in the SystemVerilog spec, so here
goes. When a module with an array port is instantiated, and the actual
argument does not match the formal port in all dimensions, is this an error?
For instance:
module comp(input [3:0] x [3:0] ...
module main ...
wire [7:0] y [3:0];
comp u1(.x(y) ...
Here, an array of 8-bit words is associated with an array of 4-bit words.
Is this an error? Or are the 8-bit words each truncated to 4-bits before
being passed in? Or something else?
Paul
This archive was generated by hypermail 2b28 : Wed Jan 16 2002 - 10:50:48 PST