Subject: RE: question about array port mismatches
From: Michael McNamara (mac@verisity.com)
Date: Wed Jan 16 2002 - 11:34:58 PST
Paul Graham writes:
> I didn't find the answer to this question in the SystemVerilog spec, so here
> goes. When a module with an array port is instantiated, and the actual
> argument does not match the formal port in all dimensions, is this an error?
> For instance:
>
> module comp(input [3:0] x [3:0] ...
>
> module main ...
> wire [7:0] y [3:0];
> comp u1(.x(y) ...
>
> Here, an array of 8-bit words is associated with an array of 4-bit words.
> Is this an error? Or are the 8-bit words each truncated to 4-bits before
> being passed in? Or something else?
>
> Paul
IMHO, It should behave analougously to it would if you passed an 8 bit
vector to a module expecting a 4 bit vector -- it should implictly
perform a partselect of the lower 4 bits of each word, when making the
connection.
[One could express this in 1364-2001 syntax as:
assign x[0] = main.y[0][3:0];
assign x[1] = main.y[1][3:0];
assign x[2] = main.y[2][3:0];
assign x[3] = main.y[3][3:0];
]
It should NOT hook the first 16 bits of y to the entire 16 bits of x!
[expressed in 1364-1995 syntax as:
assign {x[0],x[1],x[2],x[3]} = {main.y[0],main.y[1]}
]
-mac
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