Subject: Re: Parameter Interface Bugs?? Clarification?? Enhancement??
From: Michael McNamara (mac@verisity.com)
Date: Wed Jan 09 2002 - 13:19:35 PST
I stilll agree with Stuart :-)
-mac
Stuart Sutherland writes:
> Precedence: bulk
>
>
> Oops, guess I need to start using the ANSI port declarations, so I can
> remember the syntax without referring to the BNF. Let me amend my
> preference to simply say the the module parameter list should be consistent
> with the module port list. If the port list is entirely comma separated,
> the parameter list should be the same.
>
> Stu
>
> At 11:29 AM 1/9/2002, Clifford E. Cummings wrote:
> >At 11:15 AM 1/9/02 -0800, you wrote:
> >>Precedence: bulk
> >>
> >>
> >>I think the only correct answer in regards to the current 1364-2001
> >>standard is that the syntax for the placement of commas and semicolons
> >>should exactly match the syntax of port declarations with the port
> >>list. I believe that is #7 in Cliff's long list of examples. The
> >>requirement to have " ;, " in the parameter list, as in #3, is
> >>inconsistent with the ANSI C style port lists, and should be documented
> >>as an errata in the current 1364-2001 BNF.
> >
> >>At 10:45 AM 1/9/2002, Clifford E. Cummings wrote:
> >
> >>>(5) module mymodule #(parameter DEPTH=16, WIDTH=8) (...) // commas
> >>>between all parameter assignments / only one parameter keyword
> >
> >>>(7) module mymodule #(parameter DEPTH=16, AWIDTH=8; parameter BWIDTH=8)
> >>>(...) // commas between parameter lists but a semicolon to separate
> >>>another parameter keyword in the list
> >
> >If you vote for #7, you are also probably voting for #5. #5, a pure
> >comma-separated list, matches the style of the example in section 12.2 of
> >the Verilog-2001 Standard. #5 and #7 are consistent with the way
> >parameters are defined today, outside of a parameter interface. For example:
> >
> >parameter DEPTH=16,
> > AWIDTH=8,
> > BWIDTH=8;
> >
> >-OR-
> >
> >parameter DEPTH=16;
> >parameter AWIDTH=8;
> >parameter BWIDTH=8;
> >
> >The latter example (similar to #7) is somewhat inconsistent with ANSI-port
> >lists, that do not include semicolons even between input, output and inout
> >keywords. That is why I asked the question about the #7 style.
> >
> >
> >>As for the inclusion of localparams in the module parameter list, that
> >>should be postponed for a consideration in a future revision to the
> >>standard. Perhaps it could be added with SystemVerilog, or perhaps in
> >>1364-200x, or perhaps not at all. In any case, I feel it is not an
> >>errata in the current BNF.
> >>
> >>Stu
> >
> >Agreed concerning errata and inclusion of new features.
> >
> >The question is, could we make a strong case to get the big three plus
> >companies like Co-Design to support an enhanced version now that we have
> >identified a potential need. The syntax is pretty straight forward and I
> >think we could make a strong case for support of a "friendly" enhancement
> >to close holes in the Verilog-2001 implementation. If the major vendors
> >could agree to an enhanced syntax, we would then have working simulators
> >and a proven implementation to add to SystemVerilog and/or Verilog200X.
> >
> >Regards - Cliff
> >//*****************************************************************//
> >// Cliff Cummings Phone: 503-641-8446 //
> >// Sunburst Design, Inc. FAX: 503-641-8486 //
> >// 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
> >// PMB 501 Web: www.sunburst-design.com //
> >// Beaverton, OR 97005 //
> >// //
> >// Expert Verilog, Synthesis and Verification Training //
> >//*****************************************************************//
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland Sutherland HDL Inc.
> stuart@sutherland-hdl.com 22805 SW 92nd Place
> phone: 503-692-0898 Tualatin, OR 97062
> www.sutherland-hdl.com
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
This archive was generated by hypermail 2b28 : Wed Jan 09 2002 - 13:29:18 PST