Subject: Names created by generate, array of gates and array of instances allow "[]" without escaping the name
From: John Williamson (john@simucad.com)
Date: Fri May 10 2002 - 12:21:12 PDT
Hi Cliff,
The comments for Example 3 in section 12.1.3.2 on page 174 of the IEEE
2001 Verilog HDL manual show square brackets "[" and "]" in the
generated names without an escaping the name:
// Generated instance names are:
// xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1
Would you know if this is intentional?
When generated names are referenced from an SDF file, should they be
escaped in the SDF file?
Will this also apply to SystemVerilog?
Array of instances and array of gates also use the square brackets as
part of the gate or instance name after they are created. Should the
square brackets in these names be escaped?
John Williamson
Product Support Manager, Simucad
510-487-9700x206
john@simucad.com
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