Subject: RE: Names created by generate, array of gates and array of instances allow "[]" without escaping the name
From: Michael McNamara (mac@verisity.com)
Date: Fri May 10 2002 - 16:23:38 PDT
John Williamson writes:
> [1 <text/plain; us-ascii (7bit)>]
> Hi Cliff,
>
> The comments for Example 3 in section 12.1.3.2 on page 174 of the IEEE
> 2001 Verilog HDL manual show square brackets "[" and "]" in the
> generated names without an escaping the name:
>
> // Generated instance names are:
> // xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1
>
>
> Would you know if this is intentional?
>
> When generated names are referenced from an SDF file, should they be
> escaped in the SDF file?
>
> Will this also apply to SystemVerilog?
>
> Array of instances and array of gates also use the square brackets as
> part of the gate or instance name after they are created. Should the
> square brackets in these names be escaped?
>
> John Williamson
> Product Support Manager, Simucad
> 510-487-9700x206
> john@simucad.com
>
>
>
> [2 <text/html; us-ascii (quoted-printable)>]
>
Verilog 2001 introduced that concept of hierachial references through
arrayed instances, so that now it is meaningful and quite natural to
supply an array index in the middle of a hierarchial reference.
Quite nicely, as this syntax was not meaningful before, and hence also
illegal before, there is no backwards compatibility issues to contend
with. They should NOT be escaped in Verilog files. In SDF files, you
raise an issue where the new syntax must be promulgated to that
section as well.
If in Verilog 1364-2001 one escaped the name, they would instead be
refering to a local register named '\bit[0].g1 ' just as was the case
in Verilog 1364-1995
-mac
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