Subject: Reg-Removal Proposal Paper
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Sep 07 2001 - 11:14:07 PDT
Hi, All -
In our last meeting, Stu asked me to make my Reg-Removal paper available
for examination with respect to net, reg and logic data types (the paper
address net and reg data types, not logic (pre-Superlog)).
The paper can be downloaded from:
www.sunburst-design.com/papers (HDLCON 2000 paper: "A Proposal To Remove
Those Ugly Register Data Types From Verilog")
Peter -
I have also just finished putting three FSM-coding papers on my web site.
Two deal with FSM coding styles for synthesis using Verilog (SNUG
2000-Boston and SNUG 1998-San Jose) and one with a very abbreviated
fsm_perl scripting technique for generating FSMs that you might find
interesting (SNUG 1999-San Jose).
Regards - Cliff
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