Subject: Re: Interface Chapter Introduction Proposal
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Fri Sep 07 2001 - 10:51:19 PDT
I was wondering if anyone else is interested in introducing
"data channels" to Verilog++?
A channel would be similar to a (bi-directional) fifo and
would be used for connecting processes in an untimed manner.
It would be associated with a protocol, and could be bound
to an interface for synthesis purposes.
A channel would be essentially language neutral, and could
bridge between processes in different simulation environments,
e.g. a C++ process could write to one in the same way as
it uses regular file streams, and a Verilog(++) process would
see events on an interface. Usage would be somewhat similar
to TCP/IP "sockets" with some global naming scheme.
A rationale for introducing channels is that it lets high-level
designers seperate data-flow from hardware and do performance
requirement analysis on the individual paths data takes through
a system. That performance data can then be used to bind the
channels to particular interfaces during synthesis of system
busses.
Regards,
Kev.
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