Subject: Re: Interface Chapter Introduction Proposal
From: Peter Flake (flake@co-design.com)
Date: Sun Sep 09 2001 - 00:32:59 PDT
Hi Kev,
The ESS submission is focused on constructs which can be given a
well-defined timing and implementation using standard synthesis algorithms.
SUPERLOG contains several constructs to support high level modeling and in
particular the encapsulation of various communication models. For example,
queues of any length and any data type. However the synthesis of these
constructs is not guaranteed to be possible.
Even shared variable behavior can be difficult to synthesize, depending on
how it is used.
Peter.
At 10:51 AM 9/7/01 -0700, Kevin Cameron x3251 wrote:
>I was wondering if anyone else is interested in introducing
>"data channels" to Verilog++?
>
>A channel would be similar to a (bi-directional) fifo and
>would be used for connecting processes in an untimed manner.
>It would be associated with a protocol, and could be bound
>to an interface for synthesis purposes.
>
>A channel would be essentially language neutral, and could
>bridge between processes in different simulation environments,
>e.g. a C++ process could write to one in the same way as
>it uses regular file streams, and a Verilog(++) process would
>see events on an interface. Usage would be somewhat similar
>to TCP/IP "sockets" with some global naming scheme.
>
>A rationale for introducing channels is that it lets high-level
>designers seperate data-flow from hardware and do performance
>requirement analysis on the individual paths data takes through
>a system. That performance data can then be used to bind the
>channels to particular interfaces during synthesis of system
>busses.
>
>Regards,
>Kev.
This archive was generated by hypermail 2b28 : Sun Sep 09 2001 - 06:35:01 PDT