Subject: September 10 Conference Call == Plans for Face to Face Meeting on September 24.
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Sep 07 2001 - 10:43:52 PDT
Hi Everyone,
We are coming now to the final chapters of ESS. So our conference call is continuing on September 10. Our phone is still the same:
1 405 244 5555 access code 3715
Agenda:
1- Questions from last meetings.
2- Sep 10th, 2001 ESS review -- Final sections
Pages 62-66
Elaboration
Libraries
Compiler Directives
3- Interface section review - Re-written.
4- Assertion Requirement Comments.
Our plans for September 24 are the following: HDL+ Committee (Verilog++ and Assertion committees)
1- Meeting Place and Time: Start at 10:00 possibly at Mentor Graphics in San Jose.
2- Agenda:
a- Documentation for both Verilog++ and Assertion. --- STU. 1-2 hours.
b- Assertion plans, milestones and roadmap. - 2 hours.
c- Verilog++ committee (officially start at 2:00) -- no one from Co-design will be available prior to 2:00.
a- Review any items that are still unanswered.
b- Vote on acceptance of ESS subset: This is an important decision
because the ownership of ESS is officially transferred to Accellera through this vote.
c- Our next goal is Verilog Extension proposed Standard draft (first draft ) by HDLCON. What steps we need to take ? Issues List ? Assignment for proposal.
d- Final Approval is for DAC. May first we need to give the Accellera board our final proposed draft. They have one month to vote to make Verilog++ as the Accellera standard for Verilog high level design language and verification.
Develop milestones for this stage.
e- Others.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
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